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Disambiguation of "Fukaishi, Muneo"

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A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link.

, , , , , , , , and . IEEE J. Solid State Circuits, 42 (1): 111-122 (2007)

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Muneo Kitajima

Muneo Kitajima

 

Other publications of authors with the same name

A 60 GHz Power Amplifier With 14.5 dBm Saturation Power and 25% Peak PAE in CMOS 65 nm SOI., , , , , , , , and . IEEE J. Solid State Circuits, 45 (7): 1286-1294 (2010)A 20-Gb/s CMOS multichannel transmitter and receiver chip set for ultra-high-resolution digital displays., , , , , , , and . IEEE J. Solid State Circuits, 35 (11): 1611-1618 (2000)A 4.25-Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture., , , , , and . IEEE J. Solid State Circuits, 33 (12): 2139-2147 (1998)A 150 mW 8: 1 MUX and a 170 mW 1: 8 DEMUX for 2.4 gb/s optical-fiber communication systems using n-AlGaAs/i-InGaAs HJFET's., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 6 (1): 43-46 (1998)A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC., , , , and . ISSCC, page 470-471. IEEE, (2010)A 30-MHz-2.4-GHz CMOS Receiver With Integrated RF Filter and Dynamic-Range-Scalable Energy Detector for Cognitive Radio Systems., , , , , and . IEEE J. Solid State Circuits, 47 (5): 1084-1093 (2012)A Low-IF/Zero-IF Reconfigurable Analog Baseband IC With an I/Q Imbalance Cancellation Scheme., , , and . IEEE J. Solid State Circuits, 46 (3): 572-582 (2011)A high-speed low-power tri-state driver flip flop for ultra-low supply voltage GaAs heterojunction FET LSI's., , , , , , and . IEEE J. Solid State Circuits, 31 (2): 240-246 (1996)An ultra-low-power-consumption high-speed GaAs quasi-differential switch flip-flop (QD-FF)., , , , , , and . IEEE J. Solid State Circuits, 31 (9): 1361-1363 (1996)A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter., , , , and . IEEE J. Solid State Circuits, 45 (12): 2582-2590 (2010)