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Disambiguation of "Moon, Daesik"

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Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM.

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In-Hyung Moon

Baesu Moon

Philipp Moon

Oveeyen Moonian

Sangbok Moon

 

Other publications of authors with the same name

A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process., , , , , , , , , and 16 other author(s). VLSI Circuits, page 147-148. IEEE, (2018)A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 55 (1): 157-166 (2020)25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation., , , , , , , , , and 16 other author(s). ISSCC, page 430-431. IEEE, (2014)A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications., , , , , , , , , and 10 other author(s). A-SSCC, page 1-4. IEEE, (2023)22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process., , , , , , , , , and 29 other author(s). ISSCC, page 382-384. IEEE, (2020)Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM., , , , , , , , , and 25 other author(s). A-SSCC, page 153-156. IEEE, (2017)A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface., , , , , , , , , and 6 other author(s). VLSIC, page 182-. IEEE, (2015)A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration., , , , , , , , , and 14 other author(s). VLSI Circuits, page 114-. IEEE, (2019)Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 53 (10): 2906-2916 (2018)A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power., , , , , , , , , and 20 other author(s). ISSCC, page 378-380. IEEE, (2019)