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Single-fault fault-collapsing analysis in sequential logic circuits.

, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (12): 1559-1568 (1991)

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Grouped input power sensitive transition an input sequence compaction technique for power estimation., , , and . ISCAS (5), page 471-474. IEEE, (2001)Coalgebraic Division for Multilevel Logic Synthesis., and . DAC, page 438-442. IEEE Computer Society Press, (1992)Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping., , and . DAC, page 65-69. ACM Press, (1995)CB-Power: a hierarchical cell-based power characterization and estimation environment for static CMOS circuits., , and . ASP-DAC, page 189-194. IEEE, (1997)Restructuring and logic minimization for testable PLA., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (4): 488-496 (1993)Single-fault fault-collapsing analysis in sequential logic circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (12): 1559-1568 (1991)A new method for constructing IP level power model based on power sensitivity., , , and . ASP-DAC, page 135-140. ACM, (2000)Transistor reordering rules for power reduction in CMOS gates., , and . ASP-DAC, ACM, (1995)A pattern compaction technique for power estimation based on power sensitivity information., , and . ISCAS (5), page 467-470. IEEE, (2001)Fanout fault analysis for digital logic circuits., , , and . Asian Test Symposium, page 33-39. IEEE Computer Society, (1995)