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A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET., , , , , , , , , и 1 other автор(ы). CICC, стр. 1-4. IEEE, (2019)Optimization Model for Collaborative Overhaul Workshop Scheduling Problem of Multiple EMUs., , , и . HPCC/DSS/SmartCity/DependSys, стр. 1310-1317. IEEE, (2021)A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET., , , , , , , , , и 21 other автор(ы). A-SSCC, стр. 285-288. IEEE, (2018)4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET., , , , , , , , , и 2 other автор(ы). ISSCC, стр. 58-60. IEEE, (2021)Study on Optimization of Maintenance Line Operation Scheme Considering the Layout of EMU Depot., , , и . ICIAI, стр. 141-146. ACM, (2023)Optimized Model and Algorithm for Scheduling Turnaround Routes of Electric Multiple Units., , , и . HPCC/DSS/SmartCity/DependSys, стр. 1325-1330. IEEE, (2021)A 24.6-29.6GHz Hybrid Sub-Sampling PLL with Tri-State Integral Path Achieving 44fs Jitter and -254.8dB FOM in 28nm CMOS., , , , , , , , , и 1 other автор(ы). ISCAS, стр. 1-5. IEEE, (2024)A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET., , , , , , , , , и . ESSCIRC, стр. 322-325. IEEE, (2018)An Automated and Process-Portable Generator for Phase-Locked Loop., , , , , , , , , и 2 other автор(ы). DAC, стр. 511-516. IEEE, (2021)BAG2: A process-portable framework for generator-based AMS circuit design., , , , , , и . CICC, стр. 1-8. IEEE, (2018)