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Disambiguation of "Shafik, Ayman"

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A 25 Gb/s Hybrid-Integrated Silicon Photonic Source-Synchronous Receiver With Microring Wavelength Stabilization.

, , , , , , , , , , , and . IEEE J. Solid State Circuits, 51 (9): 2129-2141 (2016)

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Simone Aymanns

Charakterisierung des rgf-Regulators aus Streptococcus agalactiae. Uni Ulm, (2009)

Gerhard Aymans

Shafik Hammam

Nivien Shafik

Shafik Daoud

 

Other publications of authors with the same name

A 25GS/s 6b TI binary search ADC with soft-decision selection in 65nm CMOS., , , , , and . VLSIC, page 158-. IEEE, (2015)A 75 MHz BW 68dB DR CT-ΣΔ modulator with single amplifier biquad filter and a broadband low-power common-gate summing technique., , , , and . VLSIC, page 254-. IEEE, (2015)A 6b 1.6GS/s ADC with redundant cycle 1-tap embedded DFE in 90nm CMOS., , , , , and . CICC, page 1-4. IEEE, (2012)25Gb/s hybrid-integrated silicon photonic receiver with microring wavelength stabilization., , , , , , , , , and 1 other author(s). OFC, page 1-3. IEEE, (2015)3.6 A 10Gb/s hybrid ADC-based receiver with embedded 3-tap analog FFE and dynamically-enabled digital equalization in 65nm CMOS., , , , , and . ISSCC, page 1-3. IEEE, (2015)A 6 bit 10 GS/s TI-SAR ADC With Low-Overhead Embedded FFE/DFE Equalization for Wireline Receiver Applications., , , , and . IEEE J. Solid State Circuits, 49 (11): 2560-2574 (2014)A 75-MHz Continuous-Time Sigma-Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage., , , , and . IEEE J. Solid State Circuits, 52 (3): 657-668 (2017)A 10 Gb/s Hybrid ADC-Based Receiver With Embedded Analog and Per-Symbol Dynamically Enabled Digital Equalization., , , , , and . IEEE J. Solid State Circuits, 51 (3): 671-685 (2016)