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Disambiguation of "Anand, Bulusu"

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The impact of process-induced mechanical stress in narrow width devices and variable-taper CMOS buffer design.

, , and . Microelectron. Reliab., 53 (5): 718-724 (2013)

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Davinder Kumar Anand

Amar Frank Anand

Madhankumar Anandhakrishnan

Anand Raghavachar

Anand Roy

 

Other publications of authors with the same name

An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies., , , and . ISQED, page 665-669. IEEE, (2013)Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on Multidomain MFIM Capacitor and Negative Capacitance FDSOI., , , , , , , , , and 1 other author(s). IRPS, page 23-1. IEEE, (2022)Design and Realization of High-Speed Low-Noise Multi-Loop Skew-Based ROs Optimized for Even/Odd Multi-Phase Signals., , , , , and . IEEE Trans. Circuits Syst., 67-II (11): 2352-2356 (2020)A Variation Aware Jitter Estimation Methodology in ROs Considering Over/Undershoots in NTV Regime., , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (3): 1557-1561 (2022)Phase Noise Analysis of Separately Driven Ring Oscillators., , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (11): 4415-4428 (2022)Impact of Dummy Poly on the Process-Induced Mechanical Stress Enhanced Circuit Performance., , and . VDAT, volume 7373 of Lecture Notes in Computer Science, page 357-359. Springer, (2012)Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G Applications., , , , , , and . VLSID, page 292-296. IEEE, (2022)Tutorial T6: FinFET Device Circuit Co-design: Issues and Challenges., and . VLSID, page 12-13. IEEE Computer Society, (2015)An accurate current source model for CMOS based combinational logic cell., , , , and . ISQED, page 561-565. IEEE, (2012)Investigation of Body Bias Impact in Si/SiGe Heterojunction Line TFETs: A Physical Insight., and . ISCAS, page 1-5. IEEE, (2023)