( en | de | ru )

 

Disambiguation of "Povoa, Ricardo"

Author of the publication

copydeleteadd this publication to your clipboard
Efficient yield optimization method using a variable K-Means algorithm for analog IC sizing.

, , , , and . DATE, page 1201-1206. IEEE, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Ricardo Bernhardt

Ricardo Beilke

Ricardo Osorio

Ricardo Riegel

Paulo Ricardo

 

Other publications of authors with the same name

A new metaheuristc combining gradient models with NSGA-II to enhance analog IC synthesis., , , , and . IEEE Congress on Evolutionary Computation, page 2781-2788. IEEE, (2013)Second-order compensation BGR with low TC and high performance for space applications., , , and . Integr., (2018)Single-Stage Amplifier Biased by Voltage Combiners With Gain and Energy-Efficiency Enhancement., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (3): 266-270 (2018)A Low Noise CMOS Inverter-Based OTA for and Healthcare Signal Receivers., , , , , and . SMACD, page 161-164. IEEE, (2019)Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing., , , , , , , and . SMACD, page 13-16. IEEE, (2019)Artificial Neural Networks as an Alternative for Automatic Analog IC Placement., , , , , and . SMACD, page 1-4. IEEE, (2019)Enhanced analog and RF IC sizing methodology using PCA and NSGA-II optimization kernel., , , , and . DATE, page 660-665. IEEE, (2018)DeepPlacer: A custom integrated OpAmp placement tool using deep models., , , , and . Appl. Soft Comput., (2022)Shortening the gap between pre- and post-layout analog IC performance by reducing the LDE-induced variations with multi-objective simulated quantum annealing., , , and . Eng. Appl. Artif. Intell., (2021)Single-stage amplifiers with gain enhancement and improved energy-efficiency employing voltage-combiners., , , , and . VLSI-SoC, page 19-22. IEEE, (2013)