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AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers.

K. Koul, J. Melchert, K. Sreedhar, L. Truong, G. Nyengele, K. Zhang, Q. Liu, J. Setter, P. Chen, Y. Mei, M. Strange, R. Daly, C. Donovick, A. Carsello, T. Kong, K. Feng, D. Huff, A. Nayak, R. Setaluri, J. Thomas, N. Bhagdikar, D. Durst, Z. Myers, N. Tsiskaridze, S. Richardson, R. Bahr, K. Fatahalian, P. Hanrahan, C. Barrett, M. Horowitz, C. Torng, F. Kjolstad, and P. Raina. ACM Trans. Embed. Comput. Syst., 22 (2): 35:1-35:34 (March 2023)

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Flavio Horowitz

Alexander Horowitz

Pinchas Horowitz

Avner Horowitz

Other publications of authors with the same name

A Verilog piecewise-linear analog behavior model for mixed-signal validation.S. Liao, and M. Horowitz. CICC, page 1-5. IEEE, (2013)A high-speed, low-power 3D-SRAM architecture.H. Nho, M. Horowitz, and S. Wong. CICC, page 201-204. IEEE, (2008)Error Control and Limit Cycle Elimination in Event-Driven Piecewise Linear Analog Functional Models.B. Lim, and M. Horowitz. IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (1): 23-33 (2016)TANGRAM: Optimized Coarse-Grained Dataflow for Scalable NN Accelerators.M. Gao, X. Yang, J. Pu, M. Horowitz, and C. Kozyrakis. ASPLOS, page 807-820. ACM, (2019)Energy-Performance Tunable Logic.B. Nezamfar, E. Alon, and M. Horowitz. IEEE J. Solid State Circuits, 44 (9): 2554-2567 (2009)CMOS Image Sensors With Multi-Bucket Pixels for Computational Photography.G. Wan, X. Li, G. Agranov, M. Levoy, and M. Horowitz. IEEE J. Solid State Circuits, 47 (4): 1031-1042 (2012)Timing analysis including clock skew.D. Harris, M. Horowitz, and D. Liu. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (11): 1608-1618 (1999)False coupling exploration in timing analysis.K. Tseng, and M. Horowitz. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (11): 1795-1805 (2005)A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs.K. Chang, J. Wei, C. Huang, S. Li, K. Donnelly, M. Horowitz, Y. Li, and S. Sidiropoulos. IEEE J. Solid State Circuits, 38 (5): 747-754 (2003)A 700-Mb/s/pin CMOS signaling interface using current integrating receivers.S. Sidiropoulos, and M. Horowitz. IEEE J. Solid State Circuits, 32 (5): 681-690 (1997)

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Disambiguation of "Horowitz, Mark"

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AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers.

Please choose a person to relate this publication to

Flavio Horowitz

Alexander Horowitz

Pinchas Horowitz

Pinchas Horowitz

Avner Horowitz

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Horowitz, Mark"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers.

Please choose a person to relate this publication to

Flavio Horowitz

Alexander Horowitz

Pinchas Horowitz

Pinchas Horowitz

Avner Horowitz

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers.