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Disambiguation of "Posser, Gracieli"

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Analyzing the electromigration effects on different metal layers and different wire lengths.

, , , and . ICECS, page 682-685. IEEE, (2014)

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Diether Posser

Herbert Posser

 

Other publications of authors with the same name

Transistor sizing and gate sizing using geometric programming considering delay minimization., , , and . NEWCAS, page 85-88. IEEE, (2012)Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (4): 546-557 (2014)ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing Rules., , , , , and . ISPD, page 147-151. ACM, (2019)Reducing the number of transistors with gate clustering., , and . LASCAS, page 163-166. IEEE, (2016)A systematic approach for analyzing and optimizing cell-internal signal electromigration., , , , and . ICCAD, page 486-491. IEEE, (2014)Reducing the signal Electromigration effects on different logic gates by cell layout optimization., , , , , and . LASCAS, page 1-4. IEEE, (2015)Analyzing the electromigration effects on different metal layers and different wire lengths., , , and . ICECS, page 682-685. IEEE, (2014)A study on layout quality of automatic generated cells., , , , and . ICECS, page 651-654. IEEE, (2010)Introduction to the Special Section on Advances in Physical Design Automation., , , and . ACM Trans. Design Autom. Electr. Syst., 28 (5): 68:1-68:3 (September 2023)Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (2): 220-231 (2016)