Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime.

J. Shin, V. Zyuban, P. Bose, and T. Pinkston. ISCA, page 353-362. IEEE Computer Society, (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

V Saile

V Geoffroy

V Ustinov

V Adams

V Fendrich

Other publications of authors with the same name

Inherently Lower-Power High-Performance Superscalar Architectures.V. Zyuban, and P. Kogge. IEEE Trans. Computers, 50 (3): 268-285 (2001)Unified architecture level energy-efficiency metric.V. Zyuban. ACM Great Lakes Symposium on VLSI, page 24-29. ACM, (2002)Design methodology for semi custom processor cores.V. Zyuban, S. Asaad, T. Fox, A. Haen, D. Littrell, and J. Moreno. ACM Great Lakes Symposium on VLSI, page 448-452. ACM, (2004)A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime.J. Shin, V. Zyuban, P. Bose, and T. Pinkston. ISCA, page 353-362. IEEE Computer Society, (2008)Integrated Analysis of Power and Performance for Pipelined Microprocessors.V. Zyuban, D. Brooks, V. Srinivasan, M. Gschwind, P. Bose, P. Strenski, and P. Emma. IEEE Trans. Computers, 53 (8): 1004-1016 (2004)Low power integrated scan-retention mechanism.V. Zyuban, and S. Kosonocky. ISLPED, page 98-102. ACM, (2002)Optimization of high-performance superscalar architectures for energy efficiency.V. Zyuban, and P. Kogge. ISLPED, page 84-89. ACM, (2000)Power-efficient, reliable microprocessor architectures: modeling and design methods.P. Bose, A. Buyuktosunoglu, C. Cher, J. Darringer, M. Gupta, H. Hamann, H. Jacobson, P. Kudva, E. Kursun, N. Madan and 5 other author(s). ACM Great Lakes Symposium on VLSI, page 299-304. ACM, (2010)Microarchitectural techniques for power gating of execution units.Z. Hu, A. Buyuktosunoglu, V. Srinivasan, V. Zyuban, H. Jacobson, and P. Bose. ISLPED, page 32-37. ACM, (2004)5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth.E. Fluhr, J. Friedrich, D. Dreps, V. Zyuban, G. Still, C. Gonzalez, A. Hall, D. Hogenmiller, F. Malgioglio, R. Nett and 10 other author(s). ISSCC, page 96-97. IEEE, (2014)

BibSonomy

Disambiguation of "Zyuban, Victor V."

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime.

Please choose a person to relate this publication to

V Saile

V Geoffroy

V Ustinov

V Adams

V Fendrich

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Zyuban, Victor V."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime.

Please choose a person to relate this publication to

V Saile

V Geoffroy

V Ustinov

V Adams

V Fendrich

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime.