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Built-in test for folded programmable logic arrays., and . Microprocess. Microsystems, 11 (6): 319-329 (1987)An O(n) algorithm for width determination of power/ground routes for VLSI circuits., and . Integr., 4 (4): 345-355 (1986)Bounds on pseudoexhaustive test lengths., , and . IEEE Trans. Very Large Scale Integr. Syst., 6 (3): 420-431 (1998)Scan Path with Look Ahead Shifting (SPLASH)., and . ITC, page 696-704. IEEE Computer Society, (1986)Test Schedules for VLSI Circuits Having Built-In Test Hardware., and . IEEE Trans. Computers, 35 (4): 361-367 (1986)Procedures for Eliminating Static and Dynamic Hazards in Test Generation., and . IEEE Trans. Computers, 23 (10): 1069-1078 (1974)On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays., and . IEEE Trans. Computers, 33 (1): 21-27 (1984)Roving Emulation as a Fault Detection Mechanism., and . IEEE Trans. Computers, 35 (11): 933-939 (1986)Functional Partitioning and Simulation of Digital Circuits.. IEEE Trans. Computers, 19 (11): 1038-1046 (1970)A Note on Three-Valued Logic Simulation.. IEEE Trans. Computers, 21 (4): 399-402 (1972)