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Disambiguation of "Xie, Shaolin"

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The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips

, , , , , , , , , , and . IEEE Micro, 38 (2): 30--41 (2018)

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Shaolin Wang

Shaolin Zhou

Jian Xie

Yangpei Xie

Qian Xie

 

Other publications of authors with the same name

A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 55 (4): 933-944 (2020)Fast and Efficient Deep Sparse Multi-Strength Spiking Neural Networks with Dynamic Pruning., , , , , and . IJCNN, page 1-8. IEEE, (2018)Low Latency Spiking ConvNets with Restricted Output Training and False Spike Inhibition., , , , , and . IJCNN, page 1-8. IEEE, (2018)Extreme Datacenter Specialization for Planet-Scale Computing: ASIC Clouds., , , , , , and . ACM SIGOPS Oper. Syst. Rev., 52 (1): 96-108 (2018)The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips., , , , , , , , , and 10 other author(s). IEEE Micro, 38 (2): 30-41 (2018)A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS., , , , , , , , , and 11 other author(s). VLSI Circuits, page 30-. IEEE, (2019)A self-indexed register file for efficient arithmetical computing hardware., , , , and . CEEC, page 13-18. IEEE, (2017)MaPU: A novel mathematical computing architecture., , , , , , , , , and 16 other author(s). HPCA, page 457-468. IEEE Computer Society, (2016)The BaseJump Manycore Accelerator Network., and . CoRR, (2018)FBNA: A Fully Binarized Neural Network Accelerator., , , , , and . FPL, page 51-54. IEEE Computer Society, (2018)