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The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips

, , , , , , , , , , and . IEEE Micro, 38 (2): 30--41 (2018)

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Building Efficient Deep Neural Networks with Unitary Group Convolutions., , , , and . CoRR, (2018)Pushing the Limits of Narrow Precision Inferencing at Cloud Scale with Microsoft Floating Point., , , , , , , , , and 14 other author(s). NeurIPS, (2020)Overwrite Quantization: Opportunistic Outlier Handling for Neural Network Accelerators., , and . CoRR, (2019)ElasticFlow: A Complexity-Effective Approach for Pipelining Irregular Loop Nests., , , , and . ICCAD, page 78-85. IEEE, (2015)With Shared Microexponents, A Little Shifting Goes a Long Way., , , , , , , , , and 12 other author(s). ISCA, page 83:1-83:13. ACM, (2023)Precision Gating: Improving Neural Network Efficiency with Dynamic Dual-Precision Activations., , , , , and . ICLR, OpenReview.net, (2020)The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips., , , , , , , , , and 10 other author(s). IEEE Micro, 38 (2): 30-41 (2018)Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs., , , , , , , and . FPGA, page 15-24. ACM, (2017)Microscaling Data Formats for Deep Learning., , , , , , , , , and 23 other author(s). CoRR, (2023)A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS., , , , , , , , , and 11 other author(s). VLSI Circuits, page 30-. IEEE, (2019)