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Disambiguation of "Murray, Daniel"

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A 2× load/store pipe for a low-power 1-GHz embedded processor.

, , , , , , , , , , and . IEEE J. Solid State Circuits, 38 (11): 1857-1865 (2003)

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Kathleen Murray

Bernd Murray

Konstanze Murray

Merit Murray

Murray Spotnitz

 

Other publications of authors with the same name

A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems., , , , , , , , , and 18 other author(s). ISSCC, page 104-105. IEEE, (2007)A low-cost, 300-MHz, RISC CPU with attached media processor., , , , , , , , , and 12 other author(s). IEEE J. Solid State Circuits, 33 (11): 1829-1839 (1998)SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction., , , , , , , , and . IEEE J. Solid State Circuits, 40 (4): 895-901 (2005)A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 31 (11): 1703-1714 (1996)Document Retrieval Based on Clustered Files.. Cornell University, USA, (1972)A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor., , , , , , , , , and 9 other author(s). Digit. Tech. J., (1997)Fuzzy logic image processing., , and . Int. J. Knowl. Eng. Data Min., 6 (3): 207-233 (2019)A 2× load/store pipe for a low-power 1-GHz embedded processor., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 38 (11): 1857-1865 (2003)A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply., , , , , , , , and . IEEE J. Solid State Circuits, 41 (1): 146-151 (2006)The application of optimal control methodology to nonlinear programming problems., and . Math. Program., 21 (1): 331-347 (1981)