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A layout adjustment problem for disjoint rectangles preserving orthogonal order., , , и . Syst. Comput. Jpn., 33 (2): 31-42 (2002)Accurate Failure Rate Prediction Based on Gaussian Process Using WAT Data., , , , и . ITC, стр. 573-577. IEEE, (2022)Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection., , , , и . ATS, стр. 52-57. IEEE Computer Society, (2017)Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits., , , и . Asian Test Symposium, стр. 206-211. IEEE Computer Society, (2010)A class of sequential circuits with combinational test generation complexity under single-fault assumption., , и . Asian Test Symposium, стр. 398-403. IEEE Computer Society, (2000)Eventually Consistent Distributed Ledger Relying on Degraded Atomic Broadcast., , и . CANDAR Workshops, стр. 195-200. IEEE, (2019)An integrated DFT solution for power reduction in scan test applications by low power gating scan cell., , , , и . Integr., (2017)SelfStabilizing WaitFree Clock Synchronization with Bounded Space., , , и . OPODIS, стр. 129-144. Hermes, (1998)Design for Testability of Software-Based Self-Test for Processors., , , и . ATS, стр. 375-380. IEEE, (2006)Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects., , , , , и . ASP-DAC, стр. 442-448. ACM, (2023)