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Disambiguation of "Rylov, Sergey V."

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10+ Gb/s 90nm CMOS serial link demo in CBGA package.

, , , , , , , and . CICC, page 27-30. IEEE, (2004)

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Maxim Rylov

V Saile

V Geoffroy

Sergey Stepanov

Sergey Libert

 

Other publications of authors with the same name

An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (7): 1043-1056 (2010)An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 47 (4): 884-896 (2012)10+ gb/s 90-nm CMOS serial link demo in CBGA package., , , , , , , and . IEEE J. Solid State Circuits, 40 (9): 1987-1991 (2005)A 25 Gb/s burst-mode receiver for low latency photonic switch networks., , , , , , , and . OFC, page 1-3. IEEE, (2015)A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 41 (12): 2885-2900 (2006)A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 53 (4): 1214-1226 (2018)A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 50 (12): 3120-3132 (2015)A 5.4mW 0.0035mm2 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS., , , , , , and . ISSCC, page 98-99. IEEE, (2009)An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz., , , , and . ASYNC, page 84-95. IEEE Computer Society, (2002)A 10-Gb/s two-dimensional eye-opening monitor in 0.13-μm standard CMOS., , , , and . IEEE J. Solid State Circuits, 40 (12): 2689-2699 (2005)