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An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors.

, , , , and . DFT, page 445-453. IEEE Computer Society, (2005)

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GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (8): 991-1000 (1996)Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs., , , , and . J. Electron. Test., 23 (1): 47-54 (2007)A Functional Approach for Testing the Reorder Buffer Memory., , , and . J. Electron. Test., 30 (4): 469-481 (2014)Software-Based Testing for System Peripherals., , , , , and . J. Electron. Test., 28 (2): 189-200 (2012)A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits., , , , , and . J. Electron. Test., 33 (1): 25-36 (2017)DYRE: a DYnamic REconfigurable solution to increase GPGPU's reliability., , , and . J. Supercomput., 77 (10): 11625-11642 (2021)Guest Editors' Introduction: SBCCI 2019., and . IEEE Des. Test, 38 (4): 60-61 (2021)Expressing logical and temporal conditions in simulation environments: TPDL*., , , and . Microprocessing and Microprogramming, 26 (4): 241-252 (1989)A Reliability-aware Environment for Design Exploration for GPU Devices., , , and . DDECS, page 169-174. IEEE, (2023)RISC-V-Based Platforms for HPC: Analyzing Non-functional Properties for Future HPC and Big-Data Clusters., , , , , , , , , and 8 other author(s). SAMOS, volume 14385 of Lecture Notes in Computer Science, page 395-410. Springer, (2023)