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A physical-location-aware fault redistribution for maximum IR-drop reduction.

, , , and . ASP-DAC, page 701-706. IEEE, (2011)

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Performance-driven crosstalk elimination at post-compiler level., , , and . ISCAS, IEEE, (2006)Multi-Level Logic Synthesis Using Communication Complexity., , and . DAC, page 215-220. ACM Press, (1989)New spare cell design for IR drop minimization in Engineering Change Order., , and . DAC, page 402-407. ACM, (2009)A bus architecture for crosstalk elimination in high performance processor design., , and . CODES+ISSS, page 247-252. ACM, (2006)Switching-activity driven gate sizing and Vth assignment for low power design., , and . ASP-DAC, page 576-581. IEEE, (2006)Architectural evaluations on TSV redundancy for reliability enhancement., , , and . DATE, page 566-571. IEEE, (2017)Thread-criticality aware dynamic cache reconfiguration in multi-core system., and . ICCAD, page 413-420. IEEE, (2013)Performance-driven interconnection optimization for microarchitecture synthesis., , , and . EURO-DAC, page 118-123. IEEE Computer Society Press, (1992)On determining sensitization criterion in an iterative gate sizing process., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (2): 231-238 (1999)Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (10): 1226-1236 (1996)