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Disambiguation of "Koyanagi, Yoichi"

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A 4-Channel 1.25-10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control.

, , , , , and . IEEE J. Solid State Circuits, 44 (12): 3547-3559 (2009)

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Yoichi Kiuchi

Yoichi Otani

Yoichi Ishikawa

 

Other publications of authors with the same name

Fault Tolerant Neural Networks in Optimization Problems., and . FTCS, page 412-418. IEEE Computer Society, (1992)Design of Neural Networks to Tolerate the Mixture of Two Types of Faults., and . FTCS, page 268-277. IEEE Computer Society, (1993)Fault-Tolerant Design of Neural Networks for Solving Optimization Problems., and . IEEE Trans. Computers, 45 (12): 1450-1455 (1996)22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS., , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)The 10th Generation 16-Core SPARC64™ Processor for Mission Critical UNIX Server., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 49 (1): 32-40 (2014)A 4-Channel 1.25-10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control., , , , , and . IEEE J. Solid State Circuits, 44 (12): 3547-3559 (2009)A 10th generation 16-core SPARC64 processor for mission-critical UNIX server., , , , , , , , , and 4 other author(s). ISSCC, page 60-61. IEEE, (2013)A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel., , , , , , , , , and . ISSCC, page 346-348. IEEE, (2011)24 to 34-Gb/s ×4 multi-rate VCSEL-based optical transceiver with referenceless CDR., , , , , , , , and . OFC, page 1-3. IEEE, (2016)A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 48 (12): 3258-3267 (2013)