( en | de | ru )

 

Disambiguation of "Tamura, Hirotaka"

Author of the publication

copydeleteadd this publication to your clipboard
24 to 34-Gb/s ×4 multi-rate VCSEL-based optical transceiver with referenceless CDR.

, , , , , , , , and . OFC, page 1-3. IEEE, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Claudia Tamura

Ichiro Tamura

Hitoshi Tamura

Hirotaka Wakatsuki

Hirotaka Yoshida

 

Other publications of authors with the same name

A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process., , , , , , , , , and . CICC, page 131-134. IEEE, (2005)Jitter injection for on-chip jitter measurement in PI-based CDRs., , , and . CICC, page 1-4. IEEE, (2017)A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFE., , , , and . CICC, page 1-4. IEEE, (2014)An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection., , , , and . CICC, page 1-8. IEEE, (2013)A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology., , , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (12): 2456-2462 (2010)Charge recycling for power reduction in FPGA interconnect., , and . FPL, page 1-8. IEEE, (2013)Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit Bandwidth, and Channel ISI., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (5): 1306-1315 (2008)On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs., , , , and . IEEE J. Solid State Circuits, 50 (4): 845-855 (2015)A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 44 (12): 3580-3589 (2009)An 8-11 Gb/s Reference-Less Bang-Bang CDR Enabled by "Phase Reset"., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (7): 2129-2138 (2014)