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Disambiguation of "Mori, Toshihiko"

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24 to 34-Gb/s ×4 multi-rate VCSEL-based optical transceiver with referenceless CDR.

, , , , , , , , and . OFC, page 1-3. IEEE, (2016)

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Ryoko Mori

Toshihiko Hara

Takahito Mori

Hisako Mori

Magnus Mori

 

Other publications of authors with the same name

A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS., , , , , , , , and . VLSIC, page 1-2. IEEE, (2014)3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS., , , , , , , , , and 7 other author(s). ISSCC, page 64-65. IEEE, (2016)Low-power SRAM design using half-swing pulse-mode techniques., , , , , , , , and . IEEE J. Solid State Circuits, 33 (11): 1659-1671 (1998)Ultra-Low-Power (1.59 mW/Gbps), 56-Gbps PAM4 Operation of Si Photonic Transmitter Integrating Segmented PIN Mach-Zehnder Modulator and 28-nm CMOS Driver., , , , , , , , and . ECOC, page 1-3. IEEE, (2017)Error-Free Loopback of a Compact 25 Gb/s × 4 ch WDM Transceiver Assembly Incorporating Silicon (De)Multiplexers with Automated Phase-Error Correction., , , , , , , , , and 3 other author(s). OFC, page 1-3. IEEE, (2018)Non-binary SAR ADC with digital error correction for low power applications., , , , , , , , and . APCCAS, page 196-199. IEEE, (2010)Neural-network assistance to calculate precise eigenvalue for fitness evaluation of real product design., , , , , , and . GECCO (Companion), page 405-406. ACM, (2019)A fully integrated triple-band CMOS power amplifier for WCDMA mobile handsets., , , , , , , , , and 10 other author(s). ISSCC, page 86-88. IEEE, (2012)A 25 Gbps silicon photonic transmitter and receiver with a bridge structure for CPU interconnects., , , , , , , , , and 14 other author(s). OFC, page 1-3. IEEE, (2015)A real-time temperature-compensated CMOS RF on-chip power detector with high linearity for wireless applications., , , , and . ESSCIRC, page 349-352. IEEE, (2012)