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Creating High Performance Applications with Intel's FPGA OpenCL™ SDK.

A. Ling, U. Aydonat, S. O'Connell, D. Capalija, and G. Chiu. IWOCL, page 11:1. ACM, (2017)

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Davor Zavisic

Mark Davoren

Davor Turkovic

Davor Baros

Davor Zagorac

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Tile-based bottom-up compilation of custom mesh-of-functional-units FPGA overlays.D. Capalija, and T. Abdelrahman. FPL, page 1-8. IEEE, (2014)Microarchitecture of a Coarse-Grain Out-of-Order Superscalar Processor.D. Capalija, and T. Abdelrahman. IEEE Trans. Parallel Distributed Syst., 24 (2): 392-405 (2013)Flexibility: FPGAs and CAD in Deep Learning Acceleration.G. Chiu, A. Ling, D. Capalija, A. Bitar, and M. Abdelfattah. ISPD, page 34-41. ACM, (2018)Customizable FPGA OpenCL matrix multiply design template for deep neural networks.J. Yinger, E. Nurvitadhi, D. Capalija, A. Ling, D. Marr, K. Srivatsan, D. Moss, and S. Subhaschandra. FPT, page 259-262. IEEE, (2017)Compute Substrate for Software 2.0.J. Vasiljevic, L. Bajic, D. Capalija, S. Sokorac, D. Ignjatovic, L. Bajic, M. Trajkovic, I. Hamer, I. Matosevic, A. Cejkov and 34 other author(s). IEEE Micro, 41 (2): 50-55 (2021)In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only).E. Nurvitadhi, J. Cook, A. Mishra, D. Marr, K. Nealis, P. Colangelo, A. Ling, D. Capalija, U. Aydonat, S. Shumarayev and 1 other author(s). FPGA, page 287. ACM, (2018)An OpenCL™ Deep Learning Accelerator on Arria 10.U. Aydonat, S. O'Connell, D. Capalija, A. Ling, and G. Chiu. FPGA, page 55-64. ACM, (2017)Creating High Performance Applications with Intel's FPGA OpenCL™ SDK.A. Ling, U. Aydonat, S. O'Connell, D. Capalija, and G. Chiu. IWOCL, page 11:1. ACM, (2017)Towards Synthesis-Free JIT Compilation to Commodity FPGAs.D. Capalija, and T. Abdelrahman. FCCM, page 202-205. IEEE Computer Society, (2011)An OpenCL(TM) Deep Learning Accelerator on Arria 10.U. Aydonat, S. O'Connell, D. Capalija, A. Ling, and G. Chiu. CoRR, (2017)

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Disambiguation of "Capalija, Davor"

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Creating High Performance Applications with Intel's FPGA OpenCL™ SDK.

Please choose a person to relate this publication to

Davor Zavisic

Mark Davoren

Davor Turkovic

Davor Baros

Davor Zagorac

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Capalija, Davor"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Creating High Performance Applications with Intel's FPGA OpenCL™ SDK.

Please choose a person to relate this publication to

Davor Zavisic

Mark Davoren

Davor Turkovic

Davor Baros

Davor Zagorac

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Creating High Performance Applications with Intel's FPGA OpenCL™ SDK.