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Creating High Performance Applications with Intel's FPGA OpenCL™ SDK.

A. Ling, U. Aydonat, S. O'Connell, D. Capalija, and G. Chiu. IWOCL, page 11:1. ACM, (2017)

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Yü Chih Chiu

Chung-wai Chiu

Tiziana Chiusi

Wei-Hua Chiu

Alessandro Chiumento

Other publications of authors with the same name

Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs.G. Chiu, D. Singh, V. Manohararajah, and S. Brown. ICCAD, page 135-142. ACM, (2006)The Stratix™ 10 Highly Pipelined FPGA Architecture.D. Lewis, G. Chiu, J. Chromczak, D. Galloway, B. Gamsa, V. Manohararajah, I. Milton, T. Vanderhoek, and J. Dyken. FPGA, page 159-168. ACM, (2016)Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow.V. Manohararajah, G. Chiu, D. Singh, and S. Brown. SLIP, page 3-8. ACM, (2006)Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow.V. Manohararajah, G. Chiu, D. Singh, and S. Brown. IEEE Trans. Very Large Scale Integr. Syst., 15 (8): 895-903 (2007)An OpenCL™ Deep Learning Accelerator on Arria 10.U. Aydonat, S. O'Connell, D. Capalija, A. Ling, and G. Chiu. FPGA, page 55-64. ACM, (2017)Creating High Performance Applications with Intel's FPGA OpenCL™ SDK.A. Ling, U. Aydonat, S. O'Connell, D. Capalija, and G. Chiu. IWOCL, page 11:1. ACM, (2017)Flexibility: FPGAs and CAD in Deep Learning Acceleration.G. Chiu, A. Ling, D. Capalija, A. Bitar, and M. Abdelfattah. ISPD, page 34-41. ACM, (2018)An OpenCL(TM) Deep Learning Accelerator on Arria 10.U. Aydonat, S. O'Connell, D. Capalija, A. Ling, and G. Chiu. CoRR, (2017)Harnessing Numerical Flexibility for Deep Learning on FPGAs.A. Ling, M. Abdelfattah, S. O'Connell, A. Bitar, D. Han, R. DiCecco, S. Subhaschandra, C. Johnson, D. Denisenko, J. Fender and 1 other author(s). HEART, page 1:1-1:3. ACM, (2018)DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration.M. Abdelfattah, D. Han, A. Bitar, R. DiCecco, S. O'Connell, N. Shanker, J. Chu, I. Prins, J. Fender, A. Ling and 1 other author(s). FPL, page 411-418. IEEE Computer Society, (2018)

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Disambiguation of "Chiu, Gordon R."

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Creating High Performance Applications with Intel's FPGA OpenCL™ SDK.

Please choose a person to relate this publication to

Yü Chih Chiu

Chung-wai Chiu

Tiziana Chiusi

Wei-Hua Chiu

Alessandro Chiumento

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Chiu, Gordon R."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Creating High Performance Applications with Intel's FPGA OpenCL™ SDK.

Please choose a person to relate this publication to

Yü Chih Chiu

Chung-wai Chiu

Tiziana Chiusi

Wei-Hua Chiu

Alessandro Chiumento

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Creating High Performance Applications with Intel's FPGA OpenCL™ SDK.