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Implementation of a DC compact model for double-gate Tunnel-FET based on 2D calculations and application in circuit simulation.

, , , , , , , , and . ESSDERC, page 456-459. IEEE, (2016)

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Development of a Cinfinity-continuous small-signal model for a MOS transistor in normal operation., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (2): 163-166 (1995)Implementation of nanoscale double-gate CMOS circuits using compact advanced transport models., , , , , , and . Microelectron. J., 44 (2): 80-85 (2013)Modeling the subthreshold region of OTFTs., , , and . CCE, page 1-4. IEEE, (2011)3-D compact model for nanoscale junctionless triple-gate nanowire MOSFETs., , , and . ESSDERC, page 258-261. IEEE, (2014)Implementation of a DC compact model for double-gate Tunnel-FET based on 2D calculations and application in circuit simulation., , , , , , , , and . ESSDERC, page 456-459. IEEE, (2016)Development of a Cinfinty-Continuous Small-Signal Model for a MOS Transistor., and . ISCAS, page 193-196. IEEE, (1994)Modeling the variation of threshold voltage, mobility factor and saturation coefficient in amorphous Indium-Gallium-Zinc Oxide thin film transistors., , , , , , and . CCE, page 1-4. IEEE, (2016)Analytical modeling of RDF effects on the threshold voltage in short-channel double-gate MOSFETs., , , , , , and . MIXDES, page 127-131. IEEE, (2017)Modeling and performance study of nanoscale double gate junctionless and inversion mode MOSFETs including carrier quantization effects., , , and . Microelectron. J., 45 (9): 1220-1225 (2014)A complete and Verilog-A compatible Gate-All-Around long-channel junctionless MOSFET model implemented in CMOS inverters., , and . Microelectron. J., 46 (11): 1069-1072 (2015)