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Resonant clock mega-mesh for the IBM z13TM., , , , , , , , , and 2 other author(s). VLSIC, page 322-. IEEE, (2015)DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design., , , , , , , and . DATE, page 387-392. European Design and Automation Association, Leuven, Belgium, (2006)Technology migration technique for designs with strong RET-driven layout restrictions., , , , , , and . ISPD, page 175-182. ACM, (2005)Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (4): 509-527 (2010)The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking., , , , , , , , , and 20 other author(s). IEEE J. Solid State Circuits, 50 (1): 10-23 (2015)5.3 Wide-frequency-range resonant clock with on-the-fly mode changing for the POWER8TM microprocessor., , , , , , , , , and . ISSCC, page 100-101. IEEE, (2014)Quasi-Newton Methods for Nonlinear Programming. University of Illinois Urbana-Champaign, USA, (1997)