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An Analog Circuit Building Block Generator via Nested Multi-Fidelity Modeling.

, , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (8): 3280-3293 (2023)

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Calculating frequency-dependent inductance of VLSI interconnect by complete multiple reciprocity boundary element method., , and . ASP-DAC, page 844-849. IEEE, (2006)BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis., , , , , , , , , and 3 other author(s). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (2): 417-430 (February 2024)Efficient Approximation Algorithms for Chemical Mechanical Polishing Dummy Fill., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (3): 402-415 (2011)A Batched Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-Fidelity Modeling., , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (2): 347-359 (February 2023)An Efficient Non-Gaussian Sampling Method for High Sigma SRAM Yield Analysis., , , , , and . ACM Trans. Design Autom. Electr. Syst., 23 (3): 36:1-36:23 (2018)An Efficient Batch Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-objective Acquisition Ensemble., , , , and . CoRR, (2021)Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network., , , , , and . DATE, page 1463-1468. IEEE, (2019)High-Dimensional and Multiple-Failure-Region Importance Sampling for SRAM Yield Analysis., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (3): 806-819 (2017)An Efficient and Robust Yield Optimization Method for High-dimensional SRAM Circuits., , , , , , , and . DAC, page 1-6. IEEE, (2020)Efficient multiple starting point optimization for automated analog circuit optimization via recycling simulation data., , , , and . DATE, page 1417-1422. IEEE, (2016)