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Disambiguation of "Jia, Tianyu"

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Analyzing and Improving Fault Tolerance of Learning-Based Navigation Systems.

, , , , , and . DAC, page 841-846. IEEE, (2021)

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Jia Jia

Tianyu Zhao

Tianyu Chen

Tianyu Chen

Tianyu Wu

 

Other publications of authors with the same name

Trireme: Exploring Hierarchical Multi-Level Parallelism for Domain Specific Hardware Acceleration., , , , , , , , , and 2 other author(s). CoRR, (2022)An Adaptive Clock Scheme Exploiting Instruction-Based Dynamic Timing Slack for a GPGPU Architecture., , , and . IEEE J. Solid State Circuits, 55 (8): 2259-2269 (2020)A Dynamic Timing Enhanced DNN Accelerator With Compute-Adaptive Elastic Clock Chain Technique., , and . IEEE J. Solid State Circuits, 56 (1): 55-65 (2021)(Invited) Software-guided greybox design methodology with integrated power and clock management., , , and . MWSCAS, page 894-897. IEEE, (2017)OMU: A Probabilistic 3D Occupancy Mapping Accelerator for Real-time OctoMap at the Edge., , , , , , and . DATE, page 909-914. IEEE, (2022)A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC., , , , , , , , , and 8 other author(s). ESSCIRC, page 269-272. IEEE, (2022)Trireme: Exploration of Hierarchical Multi-level Parallelism for Hardware Acceleration., , , , , , , , , and 2 other author(s). ACM Trans. Embed. Comput. Syst., 22 (3): 53:1-53:23 (2023)An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor., , and . ESSCIRC, page 94-97. IEEE, (2018)FlexACC: A Programmable Accelerator with Application-Specific ISA for Flexible Deep Neural Network Inference., , , and . ASAP, page 266-273. IEEE, (2021)A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware., , , , , , , , , and 2 other author(s). DAC, page 1-6. IEEE, (2023)