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Disambiguation of "Natarajan, Arun"

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Introduction to the Special Issue on the 2018 IEEE International Solid-State Circuits Conference (ISSCC).

, , , , and . IEEE J. Solid State Circuits, 53 (12): 3343-3346 (2018)

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Kasyap Natarajan

Paruthiure Natarajan

Umeswaran Arunagirinathan

Natarajan Thiagarajan

Arupon Natarajan

 

Other publications of authors with the same name

Scalable Spatial Notch Suppression in Spatio-Spectral-Filtering MIMO Receiver Arrays for Digital Beamforming., , and . IEEE J. Solid State Circuits, 51 (12): 3152-3166 (2016)A fully integrated 24-GHz phased-array transmitter in CMOS., , and . IEEE J. Solid State Circuits, 40 (12): 2502-2514 (2005)A 24-GHz, +14.5-dBm fully integrated power amplifier in 0.18-μm CMOS., , and . IEEE J. Solid State Circuits, 40 (9): 1901-1908 (2005)Introduction to the Special Issue on the 2018 IEEE International Solid-State Circuits Conference (ISSCC)., , , , and . IEEE J. Solid State Circuits, 53 (12): 3343-3346 (2018)An Integral Path Self-Calibration Scheme for a Dual-Loop PLL., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 48 (4): 996-1008 (2013)W-band scalable phased arrays for imaging and communications., , , , , and . IEEE Commun. Mag., 53 (4): 196-204 (2015)Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits., , , , , , , , , and 4 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (8): 2243-2252 (2014)29.4 A 16Gb/s 3.6pJ/b wireline transceiver with phase domain equalization scheme: Integrated pulse width modulation (iPWM) in 65nm CMOS., , and . ISSCC, page 488-489. IEEE, (2017)NSDMiner: Automated discovery of Network Service Dependencies., , , , and . INFOCOM, page 2507-2515. IEEE, (2012)An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS., , , , , , , , , and 1 other author(s). VLSIC, page 176-177. IEEE, (2012)