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A hypergraph-based model for port allocation on multiple-register-file VLIW architectures., , and . Int. J. Parallel Program., 23 (6): 499-513 (1995)Guest Editorial: Special Issue on Self-Aware Systems on Chip., and . IEEE Des. Test, 35 (5): 5-6 (2018)Design Methodology for Responsive and Rrobust MIMO Control of Heterogeneous Multicores., , , , , and . IEEE Trans. Multi Scale Comput. Syst., 4 (4): 944-951 (2018)NoC-based fault-tolerant cache design in chip multiprocessors., , and . ACM Trans. Embed. Comput. Syst., 13 (3s): 115:1-115:26 (2014)System-level PVT variation-aware power exploration of on-chip communication architectures., , , and . ACM Trans. Design Autom. Electr. Syst., 14 (2): 20:1-20:25 (2009)Fast Configurable-Cache Tuning With a Unified Second-Level Cache., , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (1): 80-91 (2009)Optimal Application Mapping and Scheduling for Network-on-Chips with Computation in STT-RAM Based Router., , , and . IEEE Trans. Computers, 68 (8): 1174-1189 (2019)Real-time analysis of resource-constrained distributed systems by simulation-guided model checking., and . SIGBED Rev., 5 (1): 7 (2008)Trends in Emerging On-Chip Interconnect Technologies., and . IPSJ Trans. Syst. LSI Des. Methodol., (2008)Speculation Techniques for High Level Synthesis of Control Intensive Designs., , , , , and . DAC, page 269-272. ACM, (2001)