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Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC).

T. Devoivre, M. Lunenborg, C. Julien, J. Carrere, P. Ferreira, W. Toren, A. VandeGoor, P. Gayet, T. Berger, O. Hinsinger, P. Vannier, Y. Trouiller, Y. Rody, P. Goirand, R. Palla, I. Thomas, F. Guyader, D. Roy, B. Borot, N. Planes, S. Naudet, F. Pico, D. Duca, F. Lalanne, D. Heslinga, и M. Haond. MTDT, стр. 157-162. IEEE Computer Society, (2002)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Dolors Sabaté Planes

Nicolas Jeanvoine

Plasma-material interaction and electrode degradation in high voltage ignition dischargesN. Jeanvoine. Uni Saarbrücken, (2009)

Nicolas Rüsch

Nicolas Haas

Nicolas Trapp

Другие публикации лиц с тем же именем

Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology.P. Flatresse, B. Giraud, J. Noel, B. Pelloux-Prayer, F. Giner, D. Arora, F. Arnaud, N. Planes, J. Coz, O. Thomas и 4 other автор(ы). ISSCC, стр. 424-425. IEEE, (2013)Variability of UTBB MOSFET analog figures of merit in wide frequency range.S. Makovejev, B. Esfeh, J. Raskin, V. Kilchytska, D. Flandre, V. Barral, N. Planes, и M. Haond. ESSDERC, стр. 222-225. IEEE, (2014)28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications.R. Ranica, N. Planes, V. Huard, O. Weber, D. Noblet, D. Croain, F. Giner, S. Naudet, P. Mergault, S. Ibars и 11 other автор(ы). VLSI Circuits, стр. 1-2. IEEE, (2016)New LFN and RTN analysis methodology in 28 and 14nm FD-SOI MOSFETs.C. Theodorou, E. Ioannidis, S. Haendler, N. Planes, E. Josse, C. Dimitriadis, и G. Ghibaudo. IRPS, стр. 1. IEEE, (2015)Self-Heating in 28 FDSOI UTBB MOSFETs at Cryogenic Temperatures.L. Nyssens, A. Halder, B. Esfeh, N. Planes, M. Haond, D. Flandre, J. Raskin, и V. Kilchytska. ESSDERC, стр. 162-165. IEEE, (2019)Impact of front-back gate coupling on low frequency noise in 28 nm FDSOI MOSFETs.C. Theodorou, E. Ioannidis, S. Haendler, N. Planes, F. Arnaud, J. Jomaah, C. Dimitriadis, и G. Ghibaudo. ESSDERC, стр. 334-337. IEEE, (2012)Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC).T. Devoivre, M. Lunenborg, C. Julien, J. Carrere, P. Ferreira, W. Toren, A. VandeGoor, P. Gayet, T. Berger, O. Hinsinger и 16 other автор(ы). MTDT, стр. 157-162. IEEE Computer Society, (2002)Back-gate bias effect on UTBB-FDSOI non-linearity performance.B. Esfeh, V. Kilchytska, B. Parvais, N. Planes, M. Haond, D. Flandre, и J. Raskin. ESSDERC, стр. 148-151. IEEE, (2017)Statistical analysis of dynamic variability in 28nm FD-SOI MOSFETs.E. Ioannidis, S. Haendler, C. Theodorou, N. Planes, C. Dimitriadis, и G. Ghibaudo. ESSDERC, стр. 214-217. IEEE, (2014)Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs.F. Andrieu, M. Cassé, E. Baylac, P. Perreau, O. Nier, D. Rideau, R. Berthelon, F. Pourchon, A. Pofelski, B. Salvo и 17 other автор(ы). ESSDERC, стр. 106-109. IEEE, (2014)

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Please choose a person to relate this publication to

Dolors Sabaté Planes

Nicolas Jeanvoine

Nicolas Rüsch

Nicolas Haas

Nicolas Trapp

Другие публикации лиц с тем же именем

Disambiguation