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Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC).

T. Devoivre, M. Lunenborg, C. Julien, J. Carrere, P. Ferreira, W. Toren, A. VandeGoor, P. Gayet, T. Berger, O. Hinsinger, P. Vannier, Y. Trouiller, Y. Rody, P. Goirand, R. Palla, I. Thomas, F. Guyader, D. Roy, B. Borot, N. Planes, S. Naudet, F. Pico, D. Duca, F. Lalanne, D. Heslinga, and M. Haond. MTDT, page 157-162. IEEE Computer Society, (2002)

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Dolors Sabaté Planes

Nicolas Jeanvoine

Plasma-material interaction and electrode degradation in high voltage ignition dischargesN. Jeanvoine. Uni Saarbrücken, (2009)

Nicolas Rüsch

Nicolas Haas

Nicolas Trapp

Other publications of authors with the same name

Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology.P. Flatresse, B. Giraud, J. Noel, B. Pelloux-Prayer, F. Giner, D. Arora, F. Arnaud, N. Planes, J. Coz, O. Thomas and 4 other author(s). ISSCC, page 424-425. IEEE, (2013)Variability of UTBB MOSFET analog figures of merit in wide frequency range.S. Makovejev, B. Esfeh, J. Raskin, V. Kilchytska, D. Flandre, V. Barral, N. Planes, and M. Haond. ESSDERC, page 222-225. IEEE, (2014)28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications.R. Ranica, N. Planes, V. Huard, O. Weber, D. Noblet, D. Croain, F. Giner, S. Naudet, P. Mergault, S. Ibars and 11 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)New LFN and RTN analysis methodology in 28 and 14nm FD-SOI MOSFETs.C. Theodorou, E. Ioannidis, S. Haendler, N. Planes, E. Josse, C. Dimitriadis, and G. Ghibaudo. IRPS, page 1. IEEE, (2015)Self-Heating in 28 FDSOI UTBB MOSFETs at Cryogenic Temperatures.L. Nyssens, A. Halder, B. Esfeh, N. Planes, M. Haond, D. Flandre, J. Raskin, and V. Kilchytska. ESSDERC, page 162-165. IEEE, (2019)Impact of front-back gate coupling on low frequency noise in 28 nm FDSOI MOSFETs.C. Theodorou, E. Ioannidis, S. Haendler, N. Planes, F. Arnaud, J. Jomaah, C. Dimitriadis, and G. Ghibaudo. ESSDERC, page 334-337. IEEE, (2012)Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC).T. Devoivre, M. Lunenborg, C. Julien, J. Carrere, P. Ferreira, W. Toren, A. VandeGoor, P. Gayet, T. Berger, O. Hinsinger and 16 other author(s). MTDT, page 157-162. IEEE Computer Society, (2002)Back-gate bias effect on UTBB-FDSOI non-linearity performance.B. Esfeh, V. Kilchytska, B. Parvais, N. Planes, M. Haond, D. Flandre, and J. Raskin. ESSDERC, page 148-151. IEEE, (2017)Statistical analysis of dynamic variability in 28nm FD-SOI MOSFETs.E. Ioannidis, S. Haendler, C. Theodorou, N. Planes, C. Dimitriadis, and G. Ghibaudo. ESSDERC, page 214-217. IEEE, (2014)Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs.F. Andrieu, M. Cassé, E. Baylac, P. Perreau, O. Nier, D. Rideau, R. Berthelon, F. Pourchon, A. Pofelski, B. Salvo and 17 other author(s). ESSDERC, page 106-109. IEEE, (2014)

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Disambiguation of "Planes, Nicolas"

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URL
DOI
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Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC).

Please choose a person to relate this publication to

Dolors Sabaté Planes

Nicolas Jeanvoine

Nicolas Rüsch

Nicolas Haas

Nicolas Trapp

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Planes, Nicolas"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC).

Please choose a person to relate this publication to

Dolors Sabaté Planes

Nicolas Jeanvoine

Nicolas Rüsch

Nicolas Haas

Nicolas Trapp

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC).