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Towards the next generation of low-power test technologies.. ASICON, стр. 232-235. IEEE, (2011)Fault Diagnosis of Physical Defects Using Unknown Behavior Model., , , и . J. Comput. Sci. Technol., 20 (2): 187-194 (2005)A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells., , , , , , , , и . ITC-Asia, стр. 139-144. IEEE, (2019)Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications., , , , , , , и . ATS, стр. 43-48. IEEE, (2019)Targeted Partial-Shift For Mitigating Shift Switching Activity Hot-Spots During Scan Test., , и . PRDC, стр. 124-129. IEEE, (2019)Test Pattern Modification for Average IR-Drop Reduction., , , , и . IEEE Trans. Very Large Scale Integr. Syst., 24 (1): 38-49 (2016)Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding., , и . IEEE Trans. Very Large Scale Integr. Syst., 25 (3): 942-953 (2017)VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG., , , , , , и . IEEE Des. Test Comput., 25 (2): 122-130 (2008)High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme., , , , , , , и . IEICE Trans. Inf. Syst., 93-D (1): 2-9 (2010)A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing., , , , и . IEICE Trans. Inf. Syst., 94-D (4): 833-840 (2011)