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Disambiguation of "Li, James Chien-Mo"

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On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs.

, , , , , , , , , and . DFT, page 143-151. IEEE Computer Society, (2008)

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Chen-Chien Li

Chien-Kang Li

Michael James

Audrein James

Chieh Chien

 

Other publications of authors with the same name

GPU-based n-detect transition fault ATPG., , and . DAC, page 28:1-28:8. ACM, (2013)GPU-based timing-aware test generation for small delay defects., , , , , and . ETS, page 1-2. IEEE, (2014)An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (8): 1644-1655 (2012)Compact Test Pattern Selection for Small Delay Defect., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (6): 971-975 (2013)Diagnosis of Multiple Scan Chain Timing Faults., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (6): 1104-1116 (2008)Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits., , , , , , and . J. Electron. Test., 37 (4): 453-471 (2021)Low-IR-Drop Test Pattern Regeneration Using A Fast Predictor., , , , , , , and . ISQED, page 27-32. IEEE, (2022)Chip Performance Prediction Using Machine Learning Techniques., , , , , and . VLSI-DAT, page 1-4. IEEE, (2021)Column parity and row selection (CPRS): a BIST diagnosis technique for multiple errors in multiple scan chains., and . ITC, page 9. IEEE Computer Society, (2005)IEEE 1500 Compatible Secure Test Wrapper For Embedded IP Cores., and . ITC, page 1. IEEE Computer Society, (2008)