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Disambiguation of "Huang, Jiun-Lang"

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On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs.

, , , , , , , , , and . DFT, page 143-151. IEEE Computer Society, (2008)

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Jia-Jiun Yan

Jiun-Hao Wang

Jiun-Shan Chen

Shann-Jiun Chang

Jiun-Hung Yu

 

Other publications of authors with the same name

Diagnosing integrator leakage of single-bit first-order DeltaSigma modulator using DC input., , and . ASP-DAC, page 775-780. IEEE, (2009)A SAR ADC missing-decision level detection and removal technique., , , and . VTS, page 31-36. IEEE Computer Society, (2012)On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines.. J. Electron. Test., 22 (4-6): 387-398 (2006)LPTest: a Flexible Low-Power Test Pattern Generator., , and . J. Electron. Test., 25 (6): 323-335 (2009)Practical considerations in applying Σ-Δ modulation-based analog BIST to sampled-data systems., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 50 (9): 553-566 (2003)An IR-Drop Aware Test Pattern Generator for Scan-Based At-Speed Testing., , , , and . ATS, page 167-172. IEEE Computer Society, (2016)Design and Implementation of an FPGA-Based 16-Channel Data/Timing Formatter., , , and . ATS, page 209-214. IEEE, (2018)An On-Chip Integrator Leakage Characterization Technique and Its Application to Switched Capacitor Circuits Testing., , and . Asian Test Symposium, page 367-372. IEEE Computer Society, (2009)A Low-Cost Jitter Measurement Technique for BIST Applications., and . Asian Test Symposium, page 336-339. IEEE Computer Society, (2003)Random Jitter Testing Using Low Tap-Count Delay Lines.. Asian Test Symposium, page 100-105. IEEE Computer Society, (2005)