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Disambiguation of "Lee, Kyoungtae"

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A Ring-Oscillator Sub-Sampling PLL With Hybrid Loop Using Generator-Based Design Flow.

, , , , , , , , and . ISCAS, page 2881-2885. IEEE, (2022)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Xavier Lee Lee

Bongsoo Lee

The role of negative regulators in coordination of the Myxococcus xanthus developmental program. Uni Marburg, (2009)

Min-Hi Lee

Induction and regulation of antiviral defence mechanisms through intracytoplasmic sensors. HU Berlin, (2009)

Sangbok Lee

Nathaniel Lee

 

Other publications of authors with the same name

A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology., , , , , , , , , and 1 other author(s). VLSI Technology and Circuits, page 34-35. IEEE, (2022)A 1.8mW 2MHz-BW 66.5dB-SNDR ΔΣ ADC using VCO-based integrators with intrinsic CLA., , and . CICC, page 1-4. IEEE, (2013)A Ring-Oscillator Sub-Sampling PLL With Hybrid Loop Using Generator-Based Design Flow., , , , , , , , and . ISCAS, page 2881-2885. IEEE, (2022)A purely-VCO-based single-loop high-order continuous-time ΣΔ ADC., , , and . ISCAS, page 926-929. IEEE, (2014)34.1 A 64×64 Implantable Real-Time Single-Charged-Particle Radiation Detector for Cancer Therapy., , , , , , , and . ISSCC, page 506-508. IEEE, (2020)8 An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS., , , , , , , and . ISSCC, page 128-130. IEEE, (2021)A 0.04-mm2 0.9-mW 71-dB SNDR distributed modular AS ADC with VCO-based integrator and digital DAC calibration., , , , , and . CICC, page 1-4. IEEE, (2015)A six-port modulator based RF transmission system: Application in an OFDM environment., , , , , and . ICC, page 1-6. IEEE, (2017)A Highly Energy-Efficient Hyperdimensional Computing Processor for Wearable Multi-Modal Classification., , , , , and . BioCAS, page 1-4. IEEE, (2021)A 24.6-29.6GHz Hybrid Sub-Sampling PLL with Tri-State Integral Path Achieving 44fs Jitter and -254.8dB FOM in 28nm CMOS., , , , , , , , , and 1 other author(s). ISCAS, page 1-5. IEEE, (2024)