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Disambiguation of "Vos, Joeri De"

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A study on substrate noise coupling among TSVs in 3D chip stack.

, , , , and . IEICE Electron. Express, 15 (13): 20180460 (2018)

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Jan de Vos

Christiane de Vos

Ludovicus de Vos

An De Vos

Friederike Poche-de Vos

 

Other publications of authors with the same name

Process Complexity and Cost Considerations of Multi-Layer Die Stacks., , , , , , , , , and 5 other author(s). 3DIC, page 1-6. IEEE, (2019)Importance of alignment control during permanent bonding and its impact on via-last alignment for high density 3D interconnects., , , , , , , , , and . 3DIC, page 1-5. IEEE, (2016)A study on substrate noise coupling among TSVs in 3D chip stack., , , , and . IEICE Electron. Express, 15 (13): 20180460 (2018)Thermal experimental and modeling analysis of high power 3D packages., , , , , and . ICICDT, page 1-4. IEEE, (2015)High-density and low-leakage novel embedded 3D MIM capacitor on Si interposer., , , , , , , and . 3DIC, page 1-4. IEEE, (2016)Comparative study of 3D stacked IC and 3D interposer integration: Processing and assembly challenges., , , , , , , and . 3DIC, page 1-7. IEEE, (2014)Continuity and reliability assessment of a scalable 3×50μm and 2×40μm via-middle TSV module., , , , , , , , , and 3 other author(s). 3DIC, page 1-4. IEEE, (2016)Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects., , , , , , , , , and 1 other author(s). Microelectron. Reliab., (2017)Triple-Layering Technology for Pixel-Parallel CMOS Image Sensors Developed by Hybrid Bonding of SOI Wafers., , , , , , , , , and 2 other author(s). 3DIC, page 1-4. IEEE, (2019)Extreme wafer thinning optimization for via-last applications., , , , , , , , , and 3 other author(s). 3DIC, page 1-5. IEEE, (2016)