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Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100, 000× Reduction in Energy-to-Solution.

A. Cassidy, R. Alvarez-Icaza, F. Akopyan, J. Sawada, J. Arthur, P. Merolla, P. Datta, M. Tallada, B. Taba, A. Andreopoulos, A. Amir, S. Esser, J. Kusnitz, R. Appuswamy, C. Haymes, B. Brezzo, R. Moussalli, R. Bellofatto, C. Baks, M. Mastro, K. Schleupen, C. Cox, K. Inoue, S. Millman, N. Imam, E. McQuinn, Y. Nakamura, I. Vo, C. Guok, D. Nguyen, S. Lekuch, S. Asaad, D. Friedman, B. Jackson, M. Flickner, W. Risk, R. Manohar, and D. Modha. SC, page 27-38. IEEE Computer Society, (2014)

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Zviel Friedman

Alexander Friedman

Ariell Friedman

Michel Friedman

Daniel J Schad

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7.2 A 28GHz 32-element phased-array transceiver IC with concurrent dual polarized beams and 1.4 degree beam-steering resolution for 5G communication.B. Sadhu, Y. Tousi, J. Hallin, S. Sahl, S. Reynolds, O. Renstrom, K. Sjogren, O. Haapalahti, N. Mazor, B. Bokinge and 10 other author(s). ISSCC, page 128-129. IEEE, (2017)A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI.A. Rylyakov, J. Tierno, G. English, M. Sperling, and D. Friedman. CICC, page 431-434. IEEE, (2008)An Integral Path Self-Calibration Scheme for a Dual-Loop PLL.M. Ferriss, J. Plouchart, A. Natarajan, A. Rylyakov, B. Parker, J. Tierno, A. Babakhani, S. Yaldiz, A. Valdes-Garcia, B. Sadhu and 1 other author(s). IEEE J. Solid State Circuits, 48 (4): 996-1008 (2013)All-Digital Dynamic Self-Detection and Self-Compensation of Static Phase Offsets in Charge-Pump PLLs.Y. Liu, W. Rhee, D. Friedman, and D. Ham. ISSCC, page 176-595. IEEE, (2007)A 5.4mW 0.0035mm2 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS.K. Kim, D. Dreps, F. Ferraiolo, P. Coteus, S. Kim, S. Rylov, and D. Friedman. ISSCC, page 98-99. IEEE, (2009)Ultra-low-power analog design.D. Friedman. ISSCC, page 526-527. IEEE, (2017)An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS.M. Ferriss, J. Plouchart, A. Natarajan, A. Rylyakov, B. Parker, A. Babakhani, S. Yaldiz, B. Sadhu, A. Valdes-Garcia, J. Tierno and 1 other author(s). VLSIC, page 176-177. IEEE, (2012)Characterization of 14nm CMOS Technology At Cryogenic Temperatures Using Dense Addressable Arrays.R. Robertazzi, D. Frank, K. Tien, J. Timmerwilke, P. Song, and D. Friedman. VTS, page 1-7. IEEE, (2024)A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage.B. Sadhu, A. Valdes-Garcia, J. Plouchart, H. Ainspan, A. Gupta, M. Ferriss, M. Yeck, M. Sanduleanu, X. Gu, C. Baks and 2 other author(s). IEEE J. Solid State Circuits, 55 (6): 1516-1529 (2020)A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS.B. Kim, Y. Liu, T. Dickson, J. Bulzacchelli, and D. Friedman. IEEE J. Solid State Circuits, 44 (12): 3526-3538 (2009)

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Disambiguation of "Friedman, Daniel J."

Please choose a person to relate this publication to

Zviel Friedman

Alexander Friedman

Ariell Friedman

Michel Friedman

Daniel J Schad

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Friedman, Daniel J."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100, 000× Reduction in Energy-to-Solution.

Please choose a person to relate this publication to

Zviel Friedman

Alexander Friedman

Ariell Friedman

Michel Friedman

Daniel J Schad

Other publications of authors with the same name

Disambiguation