( en | de | ru )

 

Disambiguation of "Furuyama, Tohru"

Author of the publication

copydeleteadd this publication to your clipboard
A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 45 (1): 142-152 (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Tohru Iwai

 

Other publications of authors with the same name

A scalable MPEG-4 video codec architecture for IMT-2000 multimedia applications., , , , , , , , , and 7 other author(s). ISCAS, page 188-191. IEEE, (2000)A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes., , , , , , , , , and 23 other author(s). ISSCC, page 464-465. IEEE, (2009)Design of a 128-mb SOI DRAM using the floating body cell (FBC)., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 41 (1): 135-145 (2006)Trends and challenges of large scale embedded memories.. CICC, page 449-456. IEEE, (2004)A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 41 (1): 54-62 (2006)Variable supply-voltage scheme for low-power high-speed CMOS digital design., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 33 (3): 454-462 (1998)A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 33 (11): 1772-1780 (1998)Variable supply-voltage scheme with 95%-efficiency DC-DC converter for MPEG-4 codec., , , , and . ISLPED, page 54-59. ACM, (1999)Keynote address: Challenges of digital consumer and mobile SoC's: more Moore possible?. DATE, page 1. EDA Consortium, San Jose, CA, USA, (2007)A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes., , , , , , , , , and 23 other author(s). IEEE J. Solid State Circuits, 45 (1): 142-152 (2010)