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Minimizing Area and Energy of Deep Learning Hardware Design Using Collective Low Precision and Structured Compression., , , , , and . CoRR, (2018)High sample rate array architectures for median filters.. IEEE Trans. Signal Process., 42 (3): 707-712 (1994)Data storage time sensitive ECC schemes for MLC NAND Flash memories., , , and . ICASSP, page 2513-2517. IEEE, (2013)Articulation constrained learning with application to speech emotion recognition., , , , and . EURASIP J. Audio Speech Music. Process., (2019)A low power scheduling scheme with resources operating at multiple voltages., and . IEEE Trans. Very Large Scale Integr. Syst., 10 (1): 6-14 (2002)Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 57 (4): 986-998 (2022)Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs., , , , , and . IEEE Des. Test, 37 (6): 79-87 (2020)Impact of On-Chip Interconnect on In-Memory Acceleration of Deep Neural Networks., , , , , and . CoRR, (2021)Automated Parallel Kernel Extraction from Dynamic Application Traces., , and . CoRR, (2020)Deep Learning for Moving Blockage Prediction using Real Millimeter Wave Measurements., , , , and . CoRR, (2021)