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Computationally-redundant energy-efficient processing for y'all (CREEPY).

, , , , , , and . ICRC, page 1-8. IEEE Computer Society, (2016)

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Tackling memory access latency through DRAM row management., , , , and . MEMSYS, page 137-147. ACM, (2018)The Superstrider Architecture: Integrating Logic and Memory Towards Non-Von Neumann Computing., , , and . ICRC, page 1-8. IEEE, (2017)Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures., , , , , , , and . HPCA, page 696-709. IEEE Computer Society, (2018)Extending Moore's Law via Computationally Error-Tolerant Computing., , , , , , and . TACO, 15 (1): 8:1-8:27 (2018)Superstrider associative array architecture: Approved for unlimited unclassified release: SAND2017-7089 C., , , and . HPEC, page 1-7. IEEE, (2017)Computationally-redundant energy-efficient processing for y'all (CREEPY)., , , , , , and . ICRC, page 1-8. IEEE Computer Society, (2016)Energy efficiency limits of logic and memory., , , , , , , , , and . ICRC, page 1-8. IEEE Computer Society, (2016)Experimental Insights from the Rogues Gallery., , , , , and . ICRC, page 80-87. IEEE, (2019)A Brief Survey of Non-Residue Based Computational Error Correction., , and . CoRR, (2016)Merge Network for a Non-Von Neumann Accumulate Accelerator in a 3D Chip., , , and . ICRC, page 1-11. IEEE, (2018)