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MicroRefresh: Minimizing Refresh Overhead in DRAM Caches., , and . MEMSYS, page 350-361. ACM, (2016)A Theory for Co-Scheduling Hardware and Software Pipelines in ASIPs and Embedded Processors., , and . Des. Autom. Embed. Syst., 6 (3): 243-275 (2002)Unified Instruction Reordering and Algebraic Transformations for Minimum Cost Offset Assignment., and . SCOPES, volume 2826 of Lecture Notes in Computer Science, page 270-284. Springer, (2003)Advances in Software Pipelining., and . The Compiler Design Handbook, 2nd ed., CRC Press, (2007)Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding, , and . J. VLSI Signal Process. Syst., 44 (3): 245--267 (2006)Attempting guards in parallel: A data flow approach to execute generalized guarded commands., , and . Int. J. Parallel Program., 21 (4): 225-268 (1992)Data Flow Implementation of Generalized Guarded Commands., and . PARLE (1), volume 505 of Lecture Notes in Computer Science, page 372-389. Springer, (1991)Author Rebuttal to Rocha et al. "Comments on Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks"., and . J. Signal Process. Syst., 81 (1): 135-136 (2015)Synergistic execution of stream programs on multicores with accelerators., , and . LCTES, page 99-108. ACM, (2009)Reconciling transactional conflicts with compiler's help., and . CGO, page 53-62. ACM, (2012)