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Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization.

Z. Li, M. Sun, A. Lu, H. Ma, G. Yuan, Y. Xie, H. Tang, Y. Li, M. Leeser, Z. Wang, X. Lin, и Z. Fang. FPL, стр. 109-116. IEEE, (2022)

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Jian Xie

Yangpei Xie

Qian Xie

Mingliang Xie

Zhenwei Xie

Другие публикации лиц с тем же именем

An Incremental Placement Flow for Advanced FPGAs With Timing Awareness.Z. Lin, Y. Xie, P. Zou, S. Wang, J. Yu, и J. Chen. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (9): 3092-3103 (2022)Invited: Algorithm-Software-Hardware Co-Design for Deep Learning Acceleration.Z. Li, Y. Xie, P. Dong, O. Chen, и Y. Wang. DAC, стр. 1-4. IEEE, (2023)FPGA-aware automatic acceleration framework for vision transformer with mixed-scheme quantization: late breaking results.M. Sun, Z. Li, A. Lu, H. Ma, G. Yuan, Y. Xie, H. Tang, Y. Li, M. Leeser, Z. Wang и 2 other автор(ы). DAC, стр. 1394-1395. ACM, (2022)TAAS: a timing-aware analytical strategy for AQFP-capable placement automation.P. Dong, Y. Xie, H. Li, M. Sun, O. Chen, N. Yoshikawa, и Y. Wang. DAC, стр. 1321-1326. ACM, (2022)Late Breaking Results: An Analytical Timing-Driven Placer for Heterogeneous FPGAs*.Z. Lin, Y. Xie, G. Qian, S. Wang, J. Yu, и J. Chen. DAC, стр. 1-2. IEEE, (2020)Hardware-efficient stochastic rounding unit design for DNN training: late breaking results.S. Chang, G. Yuan, A. Lu, M. Sun, Y. Li, X. Ma, Z. Li, Y. Xie, M. Qin, X. Lin и 2 other автор(ы). DAC, стр. 1396-1397. ACM, (2022)Machine Learning Across Network-Connected FPGAs.D. Diaconu, Y. Xie, M. Güngör, S. Handagala, X. Lin, и M. Leeser. HPEC, стр. 1-7. IEEE, (2023)A Life-Cycle Energy and Inventory Analysis of Adiabatic Quantum-Flux-Parametron Circuits.M. Zabihi, Y. Xie, Z. Li, P. Dong, G. Yuan, O. Chen, M. Pedram, и Y. Wang. CoRR, (2023)Peeling the Onion: Hierarchical Reduction of Data Redundancy for Efficient Vision Transformer Training.Z. Kong, H. Ma, G. Yuan, M. Sun, Y. Xie, P. Dong, X. Meng, X. Shen, H. Tang, M. Qin и 5 other автор(ы). AAAI, стр. 8360-8368. AAAI Press, (2023)ESRU: Extremely Low-Bit and Hardware-Efficient Stochastic Rounding Unit Design for Low-Bit DNN Training.S. Chang, G. Yuan, A. Lu, M. Sun, Y. Li, X. Ma, Z. Li, Y. Xie, M. Qin, X. Lin и 2 other автор(ы). DATE, стр. 1-6. IEEE, (2023)

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Please choose a person to relate this publication to

Jian Xie

Yangpei Xie

Qian Xie

Mingliang Xie

Zhenwei Xie

Другие публикации лиц с тем же именем

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