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Symmetrical ESD trigger and pull-up using BIMOS transistor in advanced CMOS technology.

P. Galy, J. Bourgeat, J. Jimenez, N. Guitard, A. Dray, G. Troussier, B. Jacquier, and D. Marin-Cudraz. Microelectron. Reliab., 52 (9-10): 1998-2004 (2012)

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Nicolas Jeanvoine

Plasma-material interaction and electrode degradation in high voltage ignition dischargesN. Jeanvoine. Uni Saarbrücken, (2009)

Johann Jeanson

Helga Jeanblanc

Marc Jean-Richard-dit-Bressel

Antoine Jeanjean

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6T SRAM performance and power gain using double gate MOS in 28nm FDSOI technology.V. Asthana, M. Kar, J. Jimenez, S. Haendler, and P. Galy. ICICDT, page 89-92. IEEE, (2013)BIMOS transistor and its applications in ESD protection in advanced CMOS technology.P. Galy, J. Jimenez, J. Bourgeat, A. Dray, G. Troussier, B. Heitz, N. Guitard, D. Marin-Cudraz, and H. Beckrich-Ros. ICICDT, page 1-4. IEEE, (2012)Reliability impact due to high current, lattice and hot carriers temperatures on β(2×2) matrix ESD power devices for advanced CMOS technologies.P. Galy, J. Bourgeat, J. Jimenez, B. Jacquier, D. Marin-Cudraz, and S. Dudit. Microelectron. Reliab., 51 (9-11): 1608-1613 (2011)Symmetrical ESD protection for advanced CMOS technology dedicated to 100 GHz RF application.P. Galy, T. Lim, J. Bourgeat, J. Jimenez, B. Heitz, D. Marin-Cudraz, P. Benech, and J. Fournier. Microelectron. Reliab., 53 (9-11): 1284-1287 (2013)Inventory of silicon signatures induced by CDM event on deep sub-micronic CMOS-BICMOS technologies.P. Galy, S. Dudit, M. Vallet, P. Larre, M. Bilinski, E. Petit, J. Beltritti, A. Dray, J. Jimenez, F. Jezequel and 3 other author(s). Microelectron. Reliab., 50 (9-11): 1388-1392 (2010)ESD protection using BIMOS transistor in 100 GHz RF application for advanced CMOS technology.P. Galy, T. Lim, J. Jimenez, B. Heitz, P. Benech, J. Fournier, and D. Marin-Cudraz. ICICDT, page 199-202. IEEE, (2013)A full characterization of single pitch IO ESD protection based on silicon controlled rectifier and dynamic trigger circuit in CMOS 32 nm node.J. Bourgeat, P. Galy, A. Dray, J. Jimenez, D. Marin-Cudraz, and B. Jacquier. Microelectron. Reliab., 51 (9-11): 1614-1617 (2011)Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control.V. Asthana, M. Kar, J. Jimenez, J. Noel, S. Haendler, and P. Galy. ESSCIRC, page 415-418. IEEE, (2013)High swing low capacitance ESD RF protections in advanced CMOS technologies.J. Jimenez, P. Galy, J. Bourgeat, and B. Heitz. ICICDT, page 1-4. IEEE, (2012)Symmetrical ESD trigger and pull-up using BIMOS transistor in advanced CMOS technology.P. Galy, J. Bourgeat, J. Jimenez, N. Guitard, A. Dray, G. Troussier, B. Jacquier, and D. Marin-Cudraz. Microelectron. Reliab., 52 (9-10): 1998-2004 (2012)

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Disambiguation of "Jimenez, Jean"

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Symmetrical ESD trigger and pull-up using BIMOS transistor in advanced CMOS technology.

Please choose a person to relate this publication to

Nicolas Jeanvoine

Johann Jeanson

Helga Jeanblanc

Marc Jean-Richard-dit-Bressel

Antoine Jeanjean

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Jimenez, Jean"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Symmetrical ESD trigger and pull-up using BIMOS transistor in advanced CMOS technology.

Please choose a person to relate this publication to

Nicolas Jeanvoine

Johann Jeanson

Helga Jeanblanc

Marc Jean-Richard-dit-Bressel

Antoine Jeanjean

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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Chicago
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Symmetrical ESD trigger and pull-up using BIMOS transistor in advanced CMOS technology.