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Disambiguation of "Ho, Tsung-Yi"

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Lookup Table-Based Fast Reliability-Aware Sample Preparation Using Digital Microfluidic Biochips.

, , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 2708-2721 (2020)

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Tsung Ming Ho

Kun Ho Yi

Kun-ho Yi

Ky ng-ho Yi

Tsing-Tshih Tsung

 

Other publications of authors with the same name

Load-balanced clock tree synthesis with adjustable delay buffer insertion for clock skew reduction in multiple dynamic supply voltage designs., , , and . ACM Trans. Design Autom. Electr. Syst., 17 (3): 34:1-34:22 (2012)Timing-aware clock gating of pulsed-latch circuits for low power design., and . VLSI-DAT, page 1-4. IEEE, (2013)A nonlinear optimization methodology for resistor matching in analog integrated circuits., , and . VLSI-DAT, page 1-4. IEEE, (2012)Triangle-based process hotspot classification with dummification in EUVL., , , and . VLSI-DAT, page 1-4. IEEE, (2014)Autonomous vehicle routing in multiple intersections., and . ASP-DAC, page 585-590. ACM, (2019)Reliability-aware synthesis for flow-based microfluidic biochips by dynamic-device mapping., , , and . DAC, page 141:1-141:6. ACM, (2015)A logic integrated optimal pin-count design for digital microfluidic biochips., , and . DATE, page 1-6. European Design and Automation Association, (2014)Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips., , , , , , and . ASP-DAC, page 524-529. IEEE, (2017)Multi-level droplet routing in active-matrix based digital-microfluidic biochips., , , and . ASP-DAC, page 46-51. IEEE, (2018)An efficient algorithm of adjustable delay buffer insertion for clock skew minimization in multiple dynamic supply voltage designs., , and . ASP-DAC, page 825-830. IEEE, (2011)