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A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise., , , , , , , и . ISSCC, стр. 272-273. IEEE, (2013)Accurate analysis of substrate sensitivity of active transistors in an analog circuit., , , , , , , , и . ISQED, стр. 56-61. IEEE, (2011)A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques., , , , , , , и . IEEE J. Solid State Circuits, 50 (6): 1372-1381 (2015)A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits., , , , , , , , и . IEICE Trans. Electron., 94-C (4): 495-503 (2011)Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation., , , , , , , , и . IEICE Trans. Electron., 96-C (6): 884-893 (2013)Microprocessor power noise measurements with different levels of resource occupancy., и . IEICE Electron. Express, 8 (3): 182-188 (2011)On-Chip In-Place Measurements of Vth and Signal/Substrate Response of Differential Pair Transistors., , , , , , , , и . IEICE Trans. Electron., 95-C (1): 137-145 (2012)A full chip integrated power and substrate noise analysis framework for mixed-signal SoC design., , , , , , и . CICC, стр. 219-222. IEEE, (2009)