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Disambiguation of "Navabi, Zainalabedin"

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A UML Based System Level Failure Rate Assessment Technique for SoC Designs.

, , , and . VTS, page 243-248. IEEE Computer Society, (2007)

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Kambiz Navabi

Foroogh Navabi-Kermani

 

Other publications of authors with the same name

Self-Healing Many-Core Architecture: Analysis and Evaluation., and . VLSI Design, (2016)An off-line MDSI interconnect BIST incorporated in BS 1149.1., , , and . ETS, page 1-2. IEEE, (2014)On-Chip Verification of NoCs Using Assertion Processors., , , , and . DSD, page 535-538. IEEE Computer Society, (2007)Back-annotation of gate-level power properties into system level descriptions., and . NEWCAS, page 237-240. IEEE, (2014)Near-Optimal Node Selection Procedure for Aging Monitor Placement., , and . IOLTS, page 6-11. IEEE, (2018)Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models., , , and . CHDL, volume A-32 of IFIP Transactions, page 569-586. North-Holland, (1993)Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment., , and . Embedded Systems and Applications, page 139-143. CSREA Press, (2003)A Low Power BIST Architecture for FPGA Look-Up Table Testing., and . VLSI-SOC, page 394-397. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)HDLs evolve as they affect design methodology for a higher abstraction and a better integration.. DTIS, page 1. IEEE, (2015)Programmable Routing Tables for Degradable Torus-Based Networks on Chips., , and . ISCAS, page 1065-1068. IEEE, (2007)