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On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs.

, , , , , , and . ITC, page 1-10. IEEE Computer Society, (2013)

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An effective fault-injection framework for memory reliability enhancement perspectives., , , , and . DTIS, page 1-6. IEEE, (2017)Cross-layer system reliability assessment framework for hardware faults., , , , , , , , , and 4 other author(s). ITC, page 1-10. IEEE, (2016)Exploring the inherent fault tolerance of successive approximation algorithms under laser fault injection., , , and . LATS, page 1-6. IEEE, (2018)A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes., , , , , , , , and . J. Low Power Electron., 6 (2): 359-374 (2010)Formal Design Space Exploration for memristor-based crossbar architecture., , and . DDECS, page 145-150. IEEE, (2017)A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores., , , , , and . J. Electron. Test., 32 (2): 147-161 (2016)Memory-Aware Design Space Exploration for Reliability Evaluation in Computing Systems., , and . J. Electron. Test., 35 (2): 145-162 (2019)Analysis and Fault Modeling of Actual Resistive Defects in ATMEL TSTACTM eFlash Memories., , , , , , , , and . J. Electron. Test., 28 (2): 215-228 (2012)A Cross-Level Power Estimation Technique to Enhance High-Level Power Models Quality., , , , and . J. Low Power Electron., 13 (1): 10-28 (2017)Setting test conditions for improving SRAM reliability., , , , , , and . European Test Symposium, page 257. IEEE Computer Society, (2010)