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A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation.

, , , , , , , and . ISSCC, page 346-347. IEEE, (2010)

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A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation., , , , , , , and . ISSCC, page 346-347. IEEE, (2010)A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation., , , , , , , and . IEEE J. Solid State Circuits, 46 (1): 76-84 (2011)A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications., , , , , , , , , and 6 other author(s). ISSCC, page 324-606. IEEE, (2007)A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 43 (1): 172-179 (2008)Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design., , , , , , and . IEEE Des. Test Comput., 28 (1): 22-31 (2011)A methodology for yield-specific leakage estimation in memory., , , , and . CICC, page 1-4. IEEE, (2014)A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management., , , , , , , , and . ISSCC, page 456-457. IEEE, (2009)A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management., , , , , , , , and . IEEE J. Solid State Circuits, 45 (1): 103-110 (2010)