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Disambiguation of "Cherkauer, Brian S."

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A 65 nm 2-Billion Transistor Quad-Core Itanium Processor.

, , , , , , , , , , , and . IEEE J. Solid State Circuits, 44 (1): 18-31 (2009)

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Rolf-Walter Briant

Benoît Briand

Annette Brians

Ursula Brian

Brian Alexander

 

Other publications of authors with the same name

Unification of Speed, Power, Area & Reliability in CMOS Tapered Buffer Design., and . ISCAS, page 111-114. IEEE, (1994)Design of tapered buffers with local interconnect capacitance., and . IEEE J. Solid State Circuits, 30 (2): 151-155 (February 1995)A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 42 (1): 17-25 (2007)The Effects of Channel Width Tapering on the Power Dissipation of Serially Connected MOSFETs., and . ISCAS, page 2110-2113. IEEE, (1993)A 65 nm 2-Billion Transistor Quad-Core Itanium Processor., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 44 (1): 18-31 (2009)A unified design methodology for CMOS tapered buffers., and . IEEE Trans. Very Large Scale Integr. Syst., 3 (1): 99-111 (1995)A 65nm 2-Billion-Transistor Quad-Core Itanium® Processor., , , , and . ISSCC, page 92-93. IEEE, (2008)Itanium 2 Processor 6M: Higher Frequency and Larger L3 Cache., , and . IEEE Micro, 24 (2): 10-18 (2004)A 1.5-GHz 130-nm Itanium® 2 Processor with 6-MB on-die L3 cache., , , , , and . IEEE J. Solid State Circuits, 38 (11): 1887-1895 (2003)Channel width tapering of serially connected MOSFET's with emphasis on power dissipation., and . IEEE Trans. Very Large Scale Integr. Syst., 2 (1): 100-114 (1994)