( en | de | ru )

 

Disambiguation of "Inoue, Kazuki"

Author of the publication

copydeleteadd this publication to your clipboard
Evaluation of fault tolerant technique based on homogeneous FPGA architecture.

, , , , , and . VLSI-SoC, page 225-230. IEEE, (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Heide Inoue

Tomoyuki Inoue

Norman Inoue

Hiroko Inoue

Kazuo Inoue

 

Other publications of authors with the same name

FPGA Design Framework Combined with Commercial VLSI CAD., , , , , and . IEICE Trans. Inf. Syst., 96-D (8): 1602-1612 (2013)Understanding Fake Faces., , , , , and . ECCV Workshops (3), volume 11131 of Lecture Notes in Computer Science, page 566-576. Springer, (2018)An easily testable routing architecture of FPGA., , , and . VLSI-SoC, page 106-109. IEEE, (2011)An Easily Testable Routing Architecture and Prototype Chip., , , , , , , and . IEICE Trans. Inf. Syst., 95-D (2): 303-313 (2012)A Novel Local Interconnect Architecture for Variable Grain Logic Cell., , , and . ARC, volume 5453 of Lecture Notes in Computer Science, page 97-109. Springer, (2009)Evaluation of human distress by one's walking speed - toward development of early warning system for marine pilots' condition., , , and . SoSE, page 72-76. IEEE, (2011)Defect-robust FPGA architectures for intellectual property cores in system LSI., , , , , and . FPL, page 1-7. IEEE, (2013)Fault detection and avoidance of FPGA in various granularities., , , , , and . FPL, page 539-542. IEEE, (2012)A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core., , , , , , and . ACM Trans. Reconfigurable Technol. Syst., 4 (1): 5:1-5:24 (2010)A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells., , , , , , , and . IEICE Trans. Electron., 94-C (4): 548-556 (2011)